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                                                        FPGA Design

We offer a complete set of tools including tools for the design of the functionality of the FPGA and tools to simplify the placement and routing on the PCB. We also offer tools to analyze and document the timing of the designs with critical timing.

  • Aldec Active-HDL Designer is a complete, powerful environment for simulation and verification of FPGA designs. Support for most FPGA-families, and support for VHDL and Verilog with a very fast simulator.
  • Timing Designer is a powerful tool for analyzing the timing of time-critical designs. Related Timing Kits are a set of ready-made library of timing parameters for various circuits including several FPGA families.
  • Cadence® Allegro® and OrCAD FPGA Systems Planner are intended for design of printed circuit board containing one or more FPGAs with many pins. Features for planning of the pin placement and integration with the schematic system means that the routing of the PCB becomes simple and optimal.

GATEline AB l Alfred Nobels Allé 214 l 146 48 Tullinge, Sweden l Phone: +46 8 778 44 40
Copyright © 1997 - 2012 GATEline AB