To simulate and/or analyze the design is today, with the even more complex designs, absolutely necessary. To cover the different areas we offer today a number of different products:
Cadence PSpice for analog and mixed-signal simulation is available in both the OrCAD and Allegro environments and could be supplemented with various options.
ALDEC Active-HDL is a powerful simulator for VHDL and Verilog specially optimized for the simulation of FPGA designs.
Timing Designer is a powerful tool for analyzing the timing of time-critical designs. Related Design Kits are sets of ready-made libraries of timing parameters for different circuits including various FPGA families.
Cadence OrCAD Signal Explorer and Allegro PCB SI are tools for analysis and simulation of signal integrity in designs with high-density and high frequencies.