Aldec Active-HDL Designer Edition

Comprehensive FPGA design simulation and verification environment

Aldec® Active-HDL™ is the digital design entry and simulation tool with all the capabilities necessary for an FPGA designer to successfully develop and validate their FPGAs. Designers using Active-HDL have a streamlined FPGA design environment that reduces simulation and verification time all within a price that fits in their budget.

                      Block Diagram Editor          State Diagran Editor           HDL Editor                    Waveform Viewer

 

High Performance Simulation with Mixed Language Support

Active-HDL's high performance, mixed-language Baseline RTL Simulator operates at twice the speed of FPGA vendor simulators. As your design requirements increase Aldec's scalable solutions allow you to increase simulation speed to keep pace with the rise in complexity. Advanced options are also available to further optimize simulation run times and provide metrics on code coverage. In addition to VHDL and Verilog, mixed language configurations can also support SystemVerilog (design subset, assertions, or full language), SystemC, and EDIF. Active-HDL provides full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard, and the majority of the recently published IEEE 1076™-2008 Standard. Special settings allow users to select any version of these standards and enable compatibility with older versions.

 

Project Management & FPGA Vendor Interfaces

Active-HDL's extensive project management tools help you track your design progress and interface with FPGA vendor tools, allowing the user to design through a single user interface. The multi-vendor FPGA Design Flow Manager controls simulation, synthesis, and implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx®, and over 87 other popular EDA tools. The Revision Control Interface allows operation on subsequent versions of a design and revisions of design source files directly from the Active-HDL environment. In addition, design teams can track changes made to a design, view differences between multiple versions of source files, and recover previous file versions at any time.
 

Features:  

• High performance, mixed-language RTL Simulator

• Support for: VHDL, Verilog, System Verilog, SystemC

• Multiple design entry options

• Integrates seamlessly with FPGA vendor tools

• Scalable solution to support you as your verification requirements grow

• Assertion support

• Automatic testbench generation

• Advanced debugging and code coverage

• Import/export legacy designs

• Wide selection of export options, including HTML and PDF

• Supported on Microsoft® Windows® 2000, 2003, XP, and Windows Vista® operating systems

 

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Aldec Inc. is an industry-leading EDA verification company. The company specializes in design development and verification technologies for complex FPGA, ASIC, SoC and embedded system designs. GATEline is distributing Active HDL in Sweden, Norway and Finland.

www.aldec.com