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| Mönsterkort |
Cadence OrCAD FPGA System Planner
For design of PCB containing several FPGA components with high pin count
Cadence® OrCAD® FPGA System Planner is designed for designers who are developing PCB with several FPGA components with high pin count. The tool contains functions for planning of pin placement and the integration with the schematic design system means optimized interconnections on the PCB.
Like all other products in the Cadence® Allegro® and OrCAD platforms the products in the FPGA System Planner are fully scalable and in addition the tool is considering the circuits design rules when placing the pins. The tool lets the FPGA designer evaluate different FPGA architectures to find the best solution both from a technical and economical stand point.
Cadence OrCAD FPGA System Planner solves design challenges:
- Optimizing FPGA pinouts for both the FPGA and the PCB
Can simultaneously consider the logical, electrical and physical constraints of a design to create the optimal pin assignments - all within the context of component placement on a ‘virtual’ PCB
- Creating FPGA symbols that match to the FPGA’s
synthesized pinouts
Changes made to the pin locations are automatically reflected in updates to the affected symbols in Cadence OrCAD Capture / OrCAD Capture CIS and Cadence Design Entry / Cadence Design Entry HDL.
- Producing associated schematics to connect the FPGA to
the rest of the system
These schematics represent every FPGA and every component connected to those FPGAs. This feature alone can shave weeks off of a typical FPGA-based system design
- Generating the correct power connections for the FPGA
Power supply requirements can be highly complex in FPGA designs and can change depending on which signal IO standards are mapped to which pins. OrCAD FPGA System Planner identifies and connects the proper power rails for each bank in the FPGA devices
- Minimizing Engineering Change Orders (ECO) and keeping
the FPGA, logic, and PCB design teams in sync
Using OrCAD FPGA System Planner to drive the pin assignment process and manage these changes can significantly reduce the number of ECO’s and effectively eliminate back-end pin swaps
Benefits
- Reduced crossovers resulting in fewer vias and fewer PCB layers
- Improved signal integrity
- Shorter design cycles
- Fewer ECO’s
- Lower design, test, manufacturing, and end-product costs
- Improved product reliability
Integration with FPGA Vendor Tools
In addition to its integration with Cadence PCB design
technologies, the OrCAD FPGA System
Planners communicate seamlessly with FPGA design tools, generating and
reading supported FPGA vendors’ pin assignment constraint files. This
capability enables the FPGA designer to evaluate pin assignments against
the functional needs of the FPGA. Any changes made by the FPGA designer
to account for these requirements can be imported into to the tool so
that the complete set of pin assignments remains in sync. With this
integration, users can also import pin assignments into the OrCAD and
Allegro FPGA System Planners for a design started with the FPGA tools to
validate assignments with other components in a placement view.
Architecture supported:
Altera®
+ Stratix® II
+ Stratix II-GX
+ Stratix III - GX
+ Stratix IV
Xilinx®
+ CoolRunner™ II
+ CoolRunner XPLA3
+ Spartan®-3
+ Spartan-3A
+ Virtex®-4
+ Virtex-5
OrCAD är ett välkänt varumärke som bland annat innehåller Capture, PSpice och Specctra, ledande programvaror som under många år gett konstruktörer av mönsterkort oöverträffade möjligheter att snabbt utföra arbetet. OrCAD ägs av Cadence Design Systems, världens största tillverkare av EDA-programvaror och marknadsförs i Sverige, Norge, Finland och Estland av GATEline AB.
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