Cadence® OrCAD® FPGA System Planner provides a complete, scalable solution for FPGA-PCB co-design and is intended for designers of printed circuit boards containing one or more FPGAs. Features for planning pin assignment and integration with the schematic system means that the routing of the PCB becomes simple and optimal.
The FPGA designer is allowed to easily explore different FPGA architectures to achieve a system that is both technically optimized and cost effective
OrCAD FPGA System Planner solves many design problems such as:
Optimizes FPGA pinning for both the FPGA and the routing of the PCB.
Taking into account the logical, electrical and physical constraints in the design to generate an optimal pin assignment. The result is shown on a virtual PCB.
Generates a symbol that matches the FPGA pinning of the synthesized FPGA.
Amendments of pin assignments is automatically updated in the schematic symbol in Cadence OrCAD Capture/Capture CIS and Cadence Allegro Design Entry CIS/Cadence Allegro Design Entry HDL.
Produces associated schematic diagrams that connects the FPGA with the
rest of the system.
These diagrams represent each FPGA, and each component as they are connected to. Just this functionality can save weeks in a typical FPGA-based design.
Generates proper power supply to the FPGA.
The supply voltage can be very complex in an FPGA design and may vary depending on which signal standard that are mapped to the pins. Allegro FPGA System Planner identifies and connects the right voltage sources to each bank of the FPGA.
Minimizes design changes (ECO) and keeps FPGA, logic and layout
designers synchronized.
By allowing Allegro FPGA System Planner to drive the pin assignment process and take care of the changes reduces the number of ECO's, while changes of pin placement effectively is eliminated in the layout.
The benefits in brief:
- Fewer signal cross overs results in fewer vias and fewer layers of the PCB.
- Shorter design time.
- Fewer ECO's.
- Lower design, test and manufacturing costs.
- Improved reliability and quality of product
Integration with FPGA manufacturer's tools.
In addition to integration with Cadence PCB tools, OrCAD FPGA System Planner easily communicates with tools for FPGA design, generates and reads the FPGA manufacturer rule files for pin assignment. This allows the FPGA designer to evaluate pin assignment for the FPGA circuit with respect to the functional requirements. Any changes the FPGA designer is doing to meet these requirements can be imported so that all pin assignments always are in sync.
The following architectures are supported:
Altera®
+ Stratix® II
+ Stratix II GX
+ Stratix III - GX
+ Stratix IV
Xilinx®
+ Cool Runner ™ II
+ Cool runner XPLA3
+ Spartan® -3
+ Spartan-3A
+ Virtex® -4
+ Virtex-5
