Allegro PCB SI performs advanced signal analysis to define design constraints before routing and to resolve electrical performance issues throughout the design cycle, across multiple boards.

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Integrated with the Cadence® Allegro® PCB design and route suite, Allegro PCB SI provides advanced signal integrity (SI) analysis both pre- and post-layout. Operating early in the design cycle allows for “what-if” scenarios, sets more accurate design constraints, and reduces design iterations. Allegro PCB SI reads and writes directly to the editor database for fast, accurate integration of results. Along with a SPICE-based simulator, it provides behavioral modeling and an embedded field solver with a robust modeling language. Bus architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals. The Allegro PCB PI Option provides modeling of all power distribution characteristics.

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Features/Benefits

• Performs a wide variety of SI analyses.
• Reduces design errors to increase first-pass success.
• Increases constraint accuracy quickly and early in the process.
• Improves product performance through solution-space exploration.
• Explores alternative topology design in the earliest stages.
• Provides modeling and testing for multi-gigahertz signals.
• Supports S-Parameter generation from signal topologies.
• Generates estimated crosstalk tables to increase design efficiency.
• Performs post-layout verifications directly from the PCB editor.
• Provides device model creation, modification, and verification.
• Verifies multiple-board and silicon-package-board signal paths.
• Analyzes power distribution system characteristics with optional plug-in.

Version 16.5

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Datasheet

Cadence PCB Signal and Power Integrity

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Including Feature

Constraint Manager