Allegro FPGA System Planner Course

In the Allegro® FPGA System Planner course, you learn to define an FPGA system and synthesize the connections in the design. You generate a schematic and PCB Editor database so the FPGA I/O assignments can be optimized in the board environment.

In this course, you will learn:

Identify how data flows from the FPGA System Planner (FSP) to the schematic and PCB.
Create a design in FSP.
Define the protocols and interfaces in an FSP design.
Synthesize the connections in FSP protocols and interfaces.
Add terminations and external ports in an FSP design.
Generate an Allegro Design Entry HDL or Allegro Design Entry CIS schematic from your FSP design.
Export your FSP placement into the PCB Editor.
Backannotate pin swaps and design changes from the schematic and PCB Editor to FSP.

Content.

Identify how data flows from the Allegro FPGA System Planner to the schematic and PCB.
Create a design in FSP.
Define the protocols and interfaces in an FSP design.
Synthesize the connections in FSP protocols and interfaces.
Add terminations and external ports in an FSP design.
Generate an Allegro Design Entry HDL schematic from your FSP design.
Export your FSP placement to the PCB Editor.
Backannotate pin swaps and design changes from the schematic and PCB Editor to FSP.