Designers reduce board layout and placement time from weeks to minutes through CircuitSpace® AutoClustering™ technology, intelligent design (IP) reuse, and replication. Reductions in PCB design time have a direct impact on time-to-market for new products, which directly correlates to profitability.

CircuitSpace seamlessly integrates with Cadence® Allegro® PCB Editor or OrCAD® PCB Editor

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GATEline is exhibiting at S.E.E. in Älvsjö/Stockholm on April 13-15 and we hope to see you in our booth C05:48!

See What´s New in the OrCAD and Allegro product families from Cadence Design Systems as well as the products from Omnify, Valor, EMA Design Automation, Aldec and more.

Welcome!

®/SystemVerilog (design) mixed-language simulation, and a flow manager that controls simulation, synthesis, and implementation of Actel®, Altera®, Lattice®, Quicklogic®, Xilinx®, and other FPGAs.   Read more>>

GATEline adds Actie-HDL from Aldec

Aldec Active-HDL provides all the capabilities needed for FPGA designers to successfully develop and validate their FPGAs. This includes a full set of HDL design tools, HDL/Verilog

Cadence Knowledge Transfer

Cadence is hosting a series of webinars to help to increase its customers’ productivity by transferring knowledge about its technologies and methodologies in key focus areas. 

Each webinar will commence at 10.00am GMT on their given date and include a 40 minute presentation followed by 20 minutes Q&A session.

Click here to see more information on all webinars and Register.

The title on March 16th is What’s New in Allegro 16.3 PCB Editor?

Learn how to use the new features in OrCAD/Allegro version 16.3 and how to use PSpice AA! These are our two new training courses in the 2010 spring training schedule. More>>