®/SystemVerilog (design) mixed-language simulation, and a flow manager that controls simulation, synthesis, and implementation of Actel®, Altera®, Lattice®, Quicklogic®, Xilinx®, and other FPGAs.   Read more>>

GATEline adds Actie-HDL from Aldec

Aldec Active-HDL provides all the capabilities needed for FPGA designers to successfully develop and validate their FPGAs. This includes a full set of HDL design tools, HDL/Verilog