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Allegro PCB High-Speed Option For enterprise customers who design PCBs with high-speed interfaces such as DDR2, PCI Express, XAUI, Allegro PCB High-Speed Option shortens design cycle, reduces unnecessary prototype iteration and makes design cycle predictable. Allegro PCB High-Speed Option includes an extensive set of features and functionality for electrical and high-speed design rules and methodologies. It includes the ability to specify high-speed electrical rules in time domain, formula based constraints for advanced standards based interfaces such as DDRx, PCI Express Gen 3, Serial ATA 3.0 and USB 3.0. It enables constraint-driven electrical rules based PCB design flow within Allegro® PCB Designer. It offers ability to constrain and design critical high-speed signals that have very tight delay, crosstalk and matched group margins by allowing users to account for Z-axis delay through the vias or connector pins as well as accounting for delay inside the package through Package-pin delay specification. For managing return paths of these critical signals, Allegro PCB High-Speed Option include capabilities to identify trace segments that cross ground/power plane voids on adjacent layers as well as the ability to spread segments between voids based on DRC rules. In addition, Allegro PCB High-Speed Option provides back drilling capability for those designs that cannot afford to have ringing on critical high-speed signals by unused segment of a through hole via. Features:
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