TimingDesigner

TimingDesigner is the most accurate tool for static timing analysis. TimingDesigner is used to specify, analyze and document the timing of complex digital designs.

Timing Designer automates the work to specify and analyze signal relationships between digital devices in a FPGA, ASIC or on a PCB. By using TimingDesigner for specification and analysis the documentation of the timing diagrams are obtained automatically.

You can also use the TimingDesigner Design Kits containing the timing diagrams for the component which dramatically speeds up the specification phase.

Key Features:

Easy-to-use timing diagram editor enables rapid specification of design requirements including: timing constraints, cause-and-effect relationships, delays, and sequence protocols.
Dynamically linked timing spreadsheet with patented technology allows accurate modeling of complex delay and constraint effects.
Powerful timing analysis engine quickly identifies worst-case timing margins, allowing users to focus on trouble spots and make accurate design partitioning decisions.
Instant updates of intelligent timing diagrams support quick evaluation of design alternatives.
Robust project manager organizes component diagrams within a single project tree and eases the management and exchange of timing data among project team members.
Extensive import/export support eases exchange of waveform and timing data between tools used in the design flow.
Interface to Cadence Allegro PCB Signal Integrity environment.